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1. 
페이스북에서 우연히 접한 글입니다. 이력을 보면 이런 글을 쓸 사람은 아닙니다. 현재 구글에서 Deepmind를 연구하는 <a href="https://www.perfectlynormal.co.uk/" target="_blank" rel="noopener">Callum Mcdougal</a>이 쓴 <a href="https://80000hours.org/wp-content/uploads/2021/08/Quant_Trading_Guide_v0-1.pdf" target="_blank" rel="noopener">Quant Trading Guide</a>입니다. 8000 Hours라는 사이트는 채용관련한 정보를 제공하는 사이트인데 퀀트 트레이딩을 하고자 하는 구직자를 위한 글로 올린 듯 합니다.

<a href="http://smallake.kr/wp-content/uploads/2025/12/Quant-Trading-Guide.pdf">Download (PDF, 179KB)</a>
위 글에서 재미있는 부분은 아래입니다. 재능있고 멋진 사람들과 일할 수 있다, 이런 점이 좋은 것이라고 했는데… 과연 그럴지. ㅠㅠㅠ
<blockquote>Work with smart, talented people 
Thanks in part to the above point, quant trading tends to attract really smart people who are all passionate about what they do. The vibe is quite similar to a Cambridge maths cohort. More generally, if you’re doing a STEM subject from a top university and you like the people you’re studying with,there’s a good chance you’ll like the people you meet in quant trading.</blockquote>
2. 
글을 딱히 쓰지 않지만 관심을 계속 가지고 있었던 주제인 고비도매매. 위 글을 보고 그동안 관심있게 보았던 몇가지 글을 소개합니다.
첫째 FPGA. 트레이딩시장이 큰 나라에서는 보편화한 주제입니다. 한국은 아직입니다. 물론 외국인투자자들은 예외입니다. IEEE Xplore를 보면 FPGA를 이용한 고빈도매매를 다룬 논문이 많습니다.
<a href="https://ieeexplore.ieee.org/document/8279781" target="_blank" rel="noopener">Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis</a>
2017년 논문인데 2025년 논문이 있습니다. 구체적인 개발과정을 자세히 정리하고 있습니다. 논문은 <a href="https://ieeexplore.ieee.org/document/10841781" target="_blank" rel="noopener">FPGA for High-Frequency Trading: Reducing Latency in Financial Systems</a>입니다. 유료로 다운로드 받을 수 있습니다.
<blockquote>A. FPGA Hardware Platform The foundation of our HFT system is the Xilinx Virtex-7 FPGA, a high-performance platform known for its ability to process large amounts of data with minimal latency. The Virtex-7 was selected since its processing capabilities were high within low power usage, an attribute that might prove relevant in the high-frequency trading domain. The FPGAs architecture is highly flexible, allowing for the implementation of custom logic to perform specific trading operations directly on the hardware. FPGAs are particularly well-suited for HFT because they can perform multiple operations simultaneously due to their inherent parallel processing capabilities. This has been proved to be an important advantage especially in a world where decisions are made within microseconds, making or breaking a trade. In this architecture, the FPGA handles all time-critical tasks such as data acquisition, order processing, and trade execution, bypassing the need for software-level processing that would introduce additional latency.
B. Data Acquisition and Preprocessing The data acquisition module is designed to collect real-time market data feeds in multiple exchanges through a 10 Gigabit Ethernet link. Such streams contain data in the form of order book updates, trade execution reports, and other brief market overviews which must be quickly analyzed in order to keep up with competition. In our system, the FPGA is programmed to perform initial data filtering and feature extraction directly upon receiving the data. This step is important for the expansion of the algorithms dependent on the rate of the market since it sets a limitation for the volume of data set that the trading algorithm will have to analyze. By doing these operations at the hardware level, we are able to avoid additional latency that would be provided by software based data processing.
C. Trading Algorithm Implementation At the heart of the FPGA-based HFT system is the trading algorithm, implemented using Hardware Description Languages (HDLs) such as VHDL and Verilog. This algorithm is used for market analysis, trading signals recognition and trade orders generation in real time.
The algorithm leverages the FPGA’s parallel processing capabilities to evaluate multiple trading strategies concurrently, significantly reducing the decision-making time. In a conventional software-based system, trading algorithms are said to run in linear sequence, thus a lot of failure points occur where there is heavy flow of market data volume. By contrast, our FPGA-based system can execute multiple trading operations in parallel, ensuring that decisions are made within microseconds of receiving market data.
E. Latency Optimization Techniques 
Various latency optimization strategies are used within the system to achieve the HFT system’s ultra-low latency. These include:
Parallel Processing: As discussed, the FPGA’s ability to perform parallel processing allows the system to execute multiple tasks simultaneously, significantly reducing the overall time required for data processing and decision-making. 
Pipelining: Data acquisition, preprocessing, and order execution are grouped into stages, enabling the parts of the system to process data continuously, non-serially. By doing this, one is able to feed the system with continuous data flow that is otherwise characterized by high latencies. 
Hardware-Level Optimization: All critical functions, including data filtering, market analysis, and order submission, are performed directly on the FPGA hardware, bypassing the need for software- based processing. This approach rules out latency issues commonly encountered due to software run time and System calls. Low-Latency Communication: The system must interface to exchanges through a low latency Ethernet connection so that trade orders are passed to the exchanges in short order after a trading decision is made.</blockquote>
구체적으로 구현하는 내용을 보면 아래와 같습니다.
<blockquote>IV. IMPLEMENTATION
This chapter describes the practical steps taken to implement the FPGA-based High-Frequency Trading (HFT) system. It outlines the tools, technologies, and methodologies 
used to develop the system and provides insights into the challenges encountered during the implementation process.
A. Development Tools and Environment
The development of the FPGA-based HFT system was carried out using the Xilinx Vivado Design Suite, a comprehensive toolset for designing, synthesizing, and implementing FPGA logic. Vivado was chosen because it included an HLS tool to translate code like C or C++ to languages like VHDL or Verilog. The key development tools include: 
Vivado High-Level Synthesis (HLS): Implemented to speed up the development process through the ability to write code with optimized hardware within a single language.
Xilinx Intellectual Property (IP) Cores: Systematic integrated pre-baw modules included memories, user control and cache, Ethernet interfaces etc to reduce the time of system construction. 
 
Vivado Simulator: Employed for functional verification of the FPGA logic before deployment, ensuring that the system behaved as expected under different market scenarios.
The FPGA used for this project was the Xilinx Virtex-7,which provides a balance of high performance and low power consumption, making it ideal for the low-latency reequirements of HFT.</blockquote>
이러한 구현의 결과중 latency를 다음과 같습니다.
<a href="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/latency.png"><img data-recalc-dims="1" fetchpriority="high" decoding="async" src="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/latency.png?resize=542%2C287" alt="" width="542" height="287" sizes="(max-width: 542px) 100vw, 542px"></a>
MIT 학생들이 팀을 만들어 수행한 과제가 있습니다. <a href="https://web.mit.edu/6.111/volume2/www/f2019/projects/endrias_Project_Final_Report.pdf" target="_blank" rel="noopener">HFT Accelerator</a>인데 결과를 보면 FPGA를 고민하는 사람들이 한번쯤 참고하면 좋은 듯 합니다.

<a href="http://smallake.kr/wp-content/uploads/2025/12/6.111-final_-HFT-Accelerator.pdf">Download (PDF, 1.47MB)</a>
관련한 소스코드는 <a href="https://github.com/Kodoh/Orderbook" rel="noopener" target="_blank">Orderbook</a>에서 확인하실 수 있습니다.
2. 
FPGA와 관련한 주제이기도 하지만 재미있는 개념을 소개하는 글이 있습니다.
<a href="https://www.globaltrading.net/the-need-for-speed/" target="_blank" rel="noopener">The need for speed</a>
위 기사중 이런 부분이 등장합니다.
<blockquote>The hardware arms race and speculative triggering
The earlier generation of HFT relied on technology such as microwave networks to reduce latency between multiple trading locations. But in a competitive environment, even microseconds proved too slow. Specialised computer chips called Field-Programmable Gate Arrays (FPGAs) have now become the industry standard for cutting latency from microseconds to tens of nanoseconds.
As more firms entered the race, vendors stepped in offering custom integrated circuits and optimised networks. David Taylor, CEO of specialist HFT vendor Exegy explains: “Firms pushing into the 10-nanosecond realm are not just relying on FPGAs – they’re designing custom integrated circuits with breakthroughs in optical-to-electronic conversion and low-level networking to capture every precious nanosecond.”
This arms race has led to some creative tactics. Until 2018, Vincent Akkermans was a senior developer at Optiver and is now co-founder at TenFive AI, a company that develops advanced multi-agent AI applications. Before he left Optiver, Akkermans worked with the pioneers of “speculative execution” or “speculative triggering” in HFT, whereby FPGA chips allow orders to be initiated, and then, based on sub-microsecond signals, cancelled by leaving them incomplete before they have been processed by the exchange.</blockquote>
위 기사중 눈에 들어온 부분은 이 부분입니다.
<blockquote>Pioneers of “speculative execution” or “speculative triggering” in HFT</blockquote>
또다른 기사를 보면 FPGA가 만든 새로운 전략이 scout order와 Speculative Triggering이라고 합니다. 금융공학적인 전략이 아니라 물리학적 전략입니다.
<blockquote>Two interesting strategies that try to beat others to be first are scout orders and speculative triggering. Small&nbsp;scout orders&nbsp;(a loss worth it) are used to detect price changes microseconds before the competiton, and then trade on it.&nbsp;Speculative triggering&nbsp;is a technique where HFT firms employ custom packet processing in FPGAs. This approach preemptively guesses the correct trading action based on incoming bits and initiates the sending of response bits even before the full incoming packet has been processed. If the guess turns out to be incorrect, the final bits of the response checksum are deliberately altered to ensure that the exchange’s network stack discards the packet. 
<a href="https://bytepawn.com/better-be-first-99-percent-of-the-time-than-second-100-percent-of-the-time.html" rel="noopener" target="_blank">Better be first 99% of the time than second 100% of the time</a>중에서</blockquote>
Speculative는 익숙한 단어지만 speculative execution과 speculative triggering은 생소합니다. 그래서 찾아보았습니다. <a href="https://www.pico.net/blog/speculative-triggering-and-surveillance-in-trading-systems/" target="_blank" rel="noopener">Speculative Triggering and Surveillance in Trading Systems</a>은 Speculative Triggering을 이렇게 정의합니다.
<blockquote>What Is Speculative Triggering? 
Speculative triggering refers to the initiation of a trading request before all the required information is available. Traders might use early indicators, such as detecting a new market data packet, even before they’re fully serialized, to gain a latency advantage. This technique enables them to place orders slightly ahead of the competition, sometimes at the level of single-digit nanoseconds.
The downside of speculative triggering is that some of its techniques result in high levels of incomplete or corrupt network data that can interfere with other traffic. Speculative orders may be deliberately “poisoned” by corrupting packet checksums, for example. These packets travel through an exchange order entry infrastructure, causing congestion.</blockquote>
어떻게 동작하는지에 대한 Eurex의 설명입니다.
<blockquote>
<ul data-processed="true">
<li data-hveid="CAMQAA" data-processed="true">Early Indicators:&nbsp;Traders use specialized hardware, often Field-Programmable Gate Arrays (FPGAs), to detect the earliest bits of an incoming market data packet (e.g., the Ethernet preamble or the IP total length field).</li>
<li data-hveid="CAMQAQ" data-processed="true">Preemptive Action:&nbsp;Based on these early, incomplete signals, the system “speculates” the full content of the message (like price or quantity) and begins composing and sending its own order or cancellation message before the full market data packet has been received or deserialized.</li>
<li data-hveid="CAMQAg" data-processed="true">Correction Mechanism:&nbsp;If the initial speculation is incorrect, the HFT system deliberately corrupts the outgoing packet’s checksum, causing the exchange’s network infrastructure to discard the invalid message.</li>
<li data-hveid="CAMQAw" data-processed="true">Latency Advantage:&nbsp;This process allows the firm to shave off nanoseconds from their reaction time, potentially placing their orders slightly ahead of competitors who wait for the entire data packet to arrive.&nbsp;</li>
</ul>
</blockquote>
<a href="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering1.png"><img data-recalc-dims="1" decoding="async" src="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering1.png?resize=1130%2C623" alt="" width="1130" height="623" sizes="(max-width: 1130px) 100vw, 1130px"></a> 
<a href="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering2.png"><img data-recalc-dims="1" decoding="async" src="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering2.png?resize=1130%2C628" alt="" width="1130" height="628" sizes="(max-width: 1130px) 100vw, 1130px"></a> 
<a href="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering3.png"><img data-recalc-dims="1" loading="lazy" decoding="async" src="https://i0.wp.com/smallake.kr/wp-content/uploads/2025/12/triggering3.png?resize=1130%2C622" alt="" width="1130" height="622" sizes="auto, (max-width: 1130px) 100vw, 1130px"></a>

<a href="http://smallake.kr/wp-content/uploads/2025/12/Insights-into-Trading-System-Dynamics-Deutsche-Borse.pdf">Download (PDF, 2.26MB)</a>
3. 
Corrupted Speculative Triggering (CST)를 적극적으로 이용하는 그룹이 있습니다. Mosaic finance입니다. 이들이 관련한 글을 LinkedIN에 올렸습니다.

<a href="http://smallake.kr/wp-content/uploads/2025/12/How-to-gain-3.2-ns-with-Corrupted-Speculative-Triggering-CST-without-being-detected-and-increase-by-3-times-EUREX-Order-Entry-connectivity-revenues.pdf">Download (PDF, 1.51MB)</a>
위 회사의 기술에 대해서는 블록미디어가 보도하였습니다. <a href="https://www.wsj.com/finance/high-speed-traders-are-feuding-over-a-way-to-save-3-2-billionths-of-a-second-dbad6fc3" rel="noopener" target="_blank">High-Speed Traders Are Feuding Over a Way to Save 3.2 Billionths of a Second</a>를 참고로 하여 작성한 기사로 보입니다.
<blockquote>문제의 CST 전략은 기술적으로 고도로 정교하다. 유렉스의 주문 시스템은 이더넷 프로토콜을 기반으로 하며, 모든 주문은 ‘프리앰블(preamble)’이라는 신호로 시작된다. 일부 트레이딩 기업들은 이 프리앰블만을 선제적으로 전송해 거래소와의 연결을 미리 활성화시킨다. 이후 유리한 정보가 확인되면 주문 내용을 신속히 삽입하고, 반대의 경우는 의도적으로 손상된 데이터나 빈 패킷을 전송해 거래를 무효화한다.
이렇게 확보되는 시간은 단 3.2나노초, 빛이 약 30cm를 이동하는 데 걸리는 시간에 불과하다. 하지만 이 미세한 시간차가 시장보다 먼저 반응할 수 있는 결정적 기회를 제공하며, 반복될 경우 수천만 달러 단위의 차익으로 이어질 수 있다는 것이 업계의 분석이다.
예를 들어 유로스톡스50 지수 선물이 급등할 경우, 해당 정보를 3.2나노초 먼저 감지한 기업은 독일 DAX 선물을 먼저 매수하고 이후 가격 상승에 따라 차익을 실현할 수 있다. 이는 전통적인 차익거래 전략이 초고속 기술을 만나 ‘반응 시간’ 그 자체가 경쟁력으로 작용하는 구조를 잘 보여준다. 
<a href="https://www.blockmedia.co.kr/archives/1020447" rel="noopener" target="_blank">단 3.2나노초, 그들이 수억 달러를 버는 방법…초고속 트레이딩의 민낯</a>중에서</blockquote>
위와 같은 기술을 한국에서 사용할 수 있을까요? 제 생각은 ‘No’입니다. 한국 DMA주문은 바로 KRX나 NXT의 게이트웨이(FEP)로 가지 않습니다. 주문유효성 검증이라는 절차를 거쳐야 하고 이는 증권사의 책임입니다. 아마도 증권사 FEP 혹은 미니원장에서 거부당하지 않을까 합니다.

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1. 페이스북에서 우연히 접한 글입니다. 이력을 보면 이런 글을 쓸 사람은 아닙니다. 현재 구글에서 Deepmind를 연구하는 Callum Mcdougal이 쓴 Quant Trading Guide입니다. 8000 Hours라는 사이트는 채용관련한 정보를 제공하는 사이트인데 퀀트 트레이딩을 하고자 하는 구직자를 위한 글로 올린 듯 합니다. 위 글에서 재미있는 부분은 아래입니다. 재능있고 멋진 사람들과 일할 수 있다, 이런 점이 좋은 것이라고 했는데… 과연 그럴지. ㅠㅠㅠ Work with...
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오랜만의 고빈도 매매… FPGA와 Speculative Triggering first appeared on 그대안의작은호수.

오랜만의 고빈도 매매… FPGA와 Speculative Triggering

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